This invention relates to ball grid array (BGA) integrated circuit (IC) packages with multiple chips for high interconnect density.
Multi-chip IC packages are becoming more widely in the IC industry because of increased device packing density, which translates into smaller packages with reduced cost. Typical multi-chip packages have multiple chips or multi-chip modules carried by a printed wiring board. In an effort to increase device packing density, IC packages have been proposed and used with multiple chips mounted on both sides of a printed wiring board. This approach complicates the interconnection strategy in the overall assembly, but reduces by nearly one-half the footprint of the IC package.
State of the art multiple chip IC packages are typically interconnected using flip-chip solder bump technology. In increasing numbers of applications flip-chip technology has replaced wire bonding interconnect technology which has been in widespread use since the earliest days of IC packaging. However, wire bonding has advantages that remain attractive. Wire bonding techniques and wire bonding machines have been refined to the point where wire bonds are relatively inexpensive and are highly reliable. However, wire bonds are regarded as having limited use in more advanced packaging approaches, partly because wire bonds require greater pitch than is available in many state of the art packages. Thus for small pitch interconnection applications the trend in the technology has been toward solder bump interconnection approaches. However, due largely to high I/O density, packaging yield using advanced packaging techniques may suffer, and the complexity of the packaging process is increased. As a result the overall cost per bond may be relatively high. The low cost and high reliability of wire bonds makes them attractive if ways can be found to adapt wire bonding to packaging high density I/O chips.
We have developed a multiple chip ball grid array package in which the I/O density is increased by mounting active chips in the standoff space (referred to herein as the BGA gap) on the underside of the substrate inside the ball grid array (BGA). This space, usually empty, or used for power and ground through connections, is efficiently utilized for chip sites to increase the I/O packing density of the package. In the preferred embodiment, one or more logic chips are wire bonded to the top side of the BGA substrate and two or more memory chips are placed in the BGA gap on the bottom side. The term xe2x80x9cchipsxe2x80x9d in this context means either single bare die configured for flip-chip interconnect or a cluster of more than one such die that has been sawn from a wafer processed for flip-chip interconnect in a multiple IC array or a chip-scale package (CSP). Interconnections between the logic and memory chips are made using vias through the BGA substrate. If desired, efficient heat sinking of the IC chips in the BGA gap can be realized by attaching the backside of the chips to the substrate during reflow of the BGA. Heat sinking of the chip or chips on the top side of the BGA can be effected by providing a heat sink plate as a cover. The chips on the underside are typically thinned to fit into the conventional standoff for the BGA. To accommodate thicker chips, the substrate board can be shaped to provide a cavity for partially recessing the chip into the substrate.
The arrangement of the invention allows the large number of I/O interconnections for the logic chip to fan out on the BGA substrate to perimeter sites that are wire bonded to controller chip. These perimeter sites on the top of the substrate are then interconnected using vias to the chips on the underside of the substrate. This hybrid approach marries, in a simple and efficient way, the low cost and high reliability of wire bonds with the high I/O density of flip-chip technology.